Power semiconductor devices are core components of energy conversion and system power supply equipment. The performances of the power semiconductor devices directly affect the overall efficiency of the industrial applications, especially for power supply configurations of processors, communication systems and data centers in a large number of electronic products. In all kinds of power supply circuits for processors, in order to meet the requirement of a long system running time, it poses a great challenge to the entire circuit in terms of efficiency and power consumption. On the other hand, high power consumption also means temperature rise and waste of power, which threatens reliable operation of the processor system in a long run, and causes additional cost for heat dissipation for the circuit.
Presently, in power supply circuit of a server system, a data center or other types of processors, the rapid improvement of the performance of the core processor and the enhanced integration of the core processor impose high requirements on the power density and efficiency of the power supply. In such power supply circuits, since the supply voltage is low for the load such as the processor, there is a high conduction loss for the circuit which operates under a low voltage and a large current for a long time. In this case, the conduction loss includes not only the loss on the power devices, but also the loss on the metal connection in the circuit system. Accordingly, there is a demand for reducing the conduction loss in design of the devices and the circuits.
As shown in FIG. 1 is a conventional topology of a power source, which includes a power switch Q1, a power switch Q2, an input power VIN, an inductor L and a filtering capacitor Co. An ideal power chip does not have any stray parameters. While in practice, the power chip has package stray parameters Z1 and Z2 generated by an interconnect metal layer (RDL), an external pin, a package interconnection, a system board interconnection. When there is a large current flowing in the circuit, the conduction loss will be generated on Q1 and Q2 as well as on the stray parameters Z1 and Z2. With the supply voltage of the load being decreased, the voltage levels of the power devices Q1 and Q2 in the circuit are decreased, and the conduction performance of the power devices is improved, while the stay parameters Z1 and Z2 due to all of the wires and metal connections in the circuit bring an increasingly high proportion of conduction loss.
For example, for a typical 15V power device, a conduction impedance of a metal layer of the device is up to 20% of the entire impedance. In order to improve power density and efficiency, how to reduce conduction loss of other parts than the semiconductor itself and how to fully utilize the interconnect conduction path (including a metal interconnection layer inside the chip, package connection, pins and metal connection of the system board) becomes an important topic.
In order to reduce conduction loss, a highly efficient optimization method is to take full utilization of all the metal connection resources, and make current flowing evenly in time domain. As shown in FIG. 2(a) is a typical circuit in which the conduction paths are conducted in a discontinuous way, delivering power cycle by cycle. In contrast. FIG. 2(b) shows ideal evenly conducted current in which power is transferred continuously through the circuit. Although the power transferred through the two circuits is of the same amount, the conduction loss in the discontinuous conduction mode of FIG. 2(a) is significantly higher than the continuous mode in FIG. 2(b).
Therefore, there is a demand for a novel interleaved parallel circuit, a novel integrated power module and a novel integrated power chip.
The above information disclosed in the BACKGROUND is merely for better understanding of the context of the present disclosure, and may include contents that do not constitute the known prior art of those skilled in the art.